Title :
Passive Order Reduction for RLC Circuits With Delay Elements
Author :
Tseng, Wenliang ; Chen, Changzhong ; Gad, Emad ; Nakhla, Michel ; Achar, Ramachandra
Author_Institution :
Nat. Central Univ., Jhongli
Abstract :
This paper describes a new algorithm to obtain reduced-order models for large networks with delay elements. The proposed algorithm can be used in situations where delay extraction-based modeling approaches have been used to model portions of interconnects with low losses, while other portions could be modeled with large networks of lumped components. It is shown that the reduced-order model is passive by construction.
Keywords :
RLC circuits; lumped parameter networks; passive networks; RLC circuit; delay element; delay extraction-based modeling; lumped component network; passive order reduction; reduced-order model; High-speed interconnect; macromodeling; model-order reduction delay system; passivity;
Journal_Title :
Advanced Packaging, IEEE Transactions on
DOI :
10.1109/TADVP.2007.906240