• DocumentCode
    940062
  • Title

    Interfacial Fracture Investigation of Low-k Packaging Using J-Integral Methodology

  • Author

    Lee, Chang-Chun ; Huang, Tai-Chun ; Hsia, Chin-Chiu ; Chiang, Kuo-Ning

  • Author_Institution
    Nat. Tsing Hua Univ., Hsinchu
  • Volume
    31
  • Issue
    1
  • fYear
    2008
  • Firstpage
    91
  • Lastpage
    99
  • Abstract
    In order to resolve the issues of RC time delay and high power consumption, IC chips with Cu/low-k interconnects are developed to meet the foregoing requirements. However, there is a high potential that in doing so it may contribute to interfacial cracks occurring or propagating between the copper metal and the low-k dielectric material as a result of poor adhesion and lower fracture toughness, which results from the inherent mechanical imperfection of low-k materials. This fracturing problem is one of the most urgent issues for the thermomechanical reliability of Cu/low-k interconnects, and it needs to be resolved urgently. For this reason, we propose a prediction methodology of finite-element analysis (FEA) based on J-integral value estimation to investigate the interfacial fracture opportunity of low-k packages. However, the J-integral calculation is path dependent and so crucial in FEA for a crack on an interface between dissimilar materials. Therefore, various paths with an integral contour surrounding the crack tip are considered to avoid a misunderstanding of the cracking energy. All the analytic results indicate that a rectangular contour with a proper ratio of length/width, and multilayers of element close to the delaminating surfaces, is suggested for obtaining a stable J-integral value. On the other hand, the proposed methodology has been validated by a four-point bending test and compared with the relative experimental data of multi-low-k dielectric films. Moreover, under a reliable integral contour path that crack driving force predicted using the type of interfacial crack constructed by means of the element death technique, it shows good agreement with the simulated results of embedding actual crack.
  • Keywords
    bending; finite element analysis; fracture toughness; fracture toughness testing; packaging; IC chip; J-integral value estimation; RC time delay; cracking energy; element death technique; finite-element analysis; four-point bending test; high power consumption; integral contour path; integrated circuit; interfacial crack; interfacial fracture investigation; low-k packaging; multi-low-k dielectric film; prediction methodology; rectangular contour; Cu/low-k interconnects; J-integral; finite-element analysis (FEA); four-point bending test; interfacial crack; package;
  • fLanguage
    English
  • Journal_Title
    Advanced Packaging, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1521-3323
  • Type

    jour

  • DOI
    10.1109/TADVP.2007.906244
  • Filename
    4358052