Drain-bias dependence of threshold voltage stability of amorphous silicon TFTs

Author

Karim, Karim S. ; Nathan, Arokia ; Hack, Michael ; Milne, William I.

Author_Institution

Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, Canada

Volume

25

Issue

4

fYear

2004

fDate

4/1/2004 12:00:00 AM

Firstpage

188

Lastpage

190

Abstract

Amorphous silicon (a-Si:H) thin-film transistors (TFTs) used in emerging, nonswitch applications such as analog amplifiers or active loads, often have a bias at the drain terminal in addition to the gate that can alter their threshold voltage (V_T) stability performance. At small gate stress voltages (0≤V_ST≤15 V) where the defect state creation instability mechanism is dominant, the presence of a bias at the TFT drain decreases the overall shift in V_T(ΔV_T) compared to the ΔV_T in the absence of a drain bias. The measured shift in V_T appears to agree with the defect pool model that the ΔV_T is proportional to the number of induced carriers in the a-Si:H channel.

Keywords

amorphous semiconductors; elemental semiconductors; silicon; thin film transistors; Si:H; TFT drain bias; a-Si:H; active loads; amorphous silicon TFT; analog amplifiers; defect pool model; defect state creation instability mechanism; drain terminal bias; drain-bias dependence; gate stress voltage; induced carriers; metastability; nonswitch applications; stability performance; thin-film transistors; threshold voltage stability; Amorphous silicon; Circuit optimization; Computer hacking; Electrons; Metastasis; Stability; Stress; Tail; Thin film transistors; Threshold voltage;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2004.825154

Filename

1278551