• DocumentCode
    940549
  • Title

    Clock generation and distribution for the 130-nm Itanium® 2 processor with 6-MB on-die L3 cache

  • Author

    Tam, Simon ; Limaye, Rahul Dilip ; Desai, Utpal Nagarji

  • Author_Institution
    Intel Corp., Santa Clara, CA, USA
  • Volume
    39
  • Issue
    4
  • fYear
    2004
  • fDate
    4/1/2004 12:00:00 AM
  • Firstpage
    636
  • Lastpage
    642
  • Abstract
    The clock generation and distribution system for the 130-nm Itanium 2 processor operates at 1.5 GHz with a skew of 24 ps. The Itanium 2 processor features 6 MB of on-die L3 cache and has a die size of 374 mm2. Fuse-based clock de-skew enables post-silicon clock optimization to gain higher frequency. This paper describes the clock generation, global clock distribution, local clocking, and the clock skew optimization feature.
  • Keywords
    CMOS digital integrated circuits; cache storage; circuit optimisation; microprocessor chips; 1.5 GHz; 130 nm; 6 MB; CMOS process; Itanium 2 processor; clock generation; clock skew optimization feature; fuse-based clock de-skew; global clock distribution; local clocking; on-die L3 cache; post-silicon clock optimization; Aluminum; CMOS process; Clocks; Copper; Frequency; Geometry; Helium; Integrated circuit interconnections; Microprocessors; Wire;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.2004.825121
  • Filename
    1278582
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=940549