Performance of MVTL OR-AND gates when data precedes bias

A six-stage shift register based on modified-variable-threshold-logic (MVTL) OR-AND gates using 90 Nb/Al-Al/sub 2/O/sub 3//Nb Josephson junctions has been fabricated and tested up to 3.0 GHz. Bias current margins of the shift register were measured to be +or-26% at 200 MHz and below, +or-11% at 2.2 GHz, and +or-1.2% at 3.0 GHz. Calculation of the lobe plots for the OR gate shows that the expected margin is +or-26% when the control current (data) precedes the bias current (clock), and when no appreciable control current is injected into the superconducting quantum interference device (SQUID) loop via the injector junction. Special taps were included in the circuit so that the switching action of each of the 18 gates could be monitored in detail without disturbing the high-speed operation of the circuit.<>