Title :
A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning
Author :
Chen, Tung-Chieh ; Chang, Yao-Wen ; Lin, Shyh-Chang
Author_Institution :
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei
Abstract :
We present in this paper a new interconnect-driven multilevel floorplanner, called interconnect-driven multilevel-floorplanning framework (IMF), to handle large-scale building-module designs. Unlike the traditional multilevel framework that adopts the ldquoLambda-shapedrdquo framework (inaccurately called the ldquoV-cyclerdquo framework in the literature): bottom-up coarsening followed by top-down uncoarsening, the IMF, in contrast, works in the ldquoV-shapedrdquo manner: top-down uncoarsening (partitioning) followed by bottom-up coarsening (merging). The top-down partitioning stage iteratively partitions the floorplan region based on min-cut bipartitioning with exact net-weight modeling to reduce the number of global interconnections and, thus, the total wirelength. Then, the bottom-up merging stage iteratively applies fixed-outline floorplanning using simulated annealing for all regions and merges two neighboring regions recursively. Experimental results show that the IMF obtains the best published fixed-outline floorplanning results with the smallest average wirelength for the Microelectronics Center of North Carolina/Gigascale Systems Research Center benchmarks. In particular, IMF scales very well as the circuit size increases. The V-shaped multilevel framework outperforms the Lambda-shaped one in the optimization of global circuit effects, such as interconnection and crosstalk optimization, since the V-shaped framework considers the global configuration first and then processes down to local ones level by level, and thus, the global effects can be handled at earlier stages. The V-shaped multilevel framework is general and, thus, can be readily applied to other problems.
Keywords :
circuit optimisation; integrated circuit design; integrated circuit interconnections; iterative methods; large scale integration; modules; nanoelectronics; simulated annealing; Gigascale Systems Research Center benchmarks; IMF scales; Microelectronics Center of North Carolina; V-shaped multilevel framework; crosstalk optimization; fixed-outline floorplanning; global circuit optimization; interconnect-driven multilevel floorplanning framework; iterative methods; large-scale building-module designs; merging stage; mincut bipartitioning; net-weight modeling; partitioning stage; simulated annealing; Floorplanning; floorplanning; multilevel framework; partitioning; physical design; simulated annealing; simulated annealing (SA);
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2007.907065