• DocumentCode
    942461
  • Title

    Modelling technique for an f.e.t. chip

  • Author

    Ajose, S.O. ; Mathews, N.A.

  • Author_Institution
    University of Lagos, Electrical Engineering Department, Lagos, Nigeria
  • Volume
    13
  • Issue
    17
  • fYear
    1977
  • Firstpage
    511
  • Lastpage
    512
  • Abstract
    A technique for modelling an f.e.t. chip is presented. First, the device is characterised in its 2-port S-parameters. Then, by choosing a suitable equivalent circuit and reasonable starting values, a simplex optimisation procedure is employed to obtain optimum component values for the equivalent circuit.
  • Keywords
    equivalent circuits; field effect transistors; semiconductor device models; 2-port S-parameters; simplex optimisation;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19770372
  • Filename
    4240500
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=942461