Sub-1/4-μm dual-gate CMOS technology using in-situ doped polysilicon for nMOS and pMOS gates

Author

Okazaki, Yukio ; Kobayashi, Toshio ; Inokawa, Hiroshi ; Nakayama, Satoshi ; Miyake, Masayasu ; Morimoto, Takashi ; Yamamoto, Yousuke

Author_Institution

NTT LSI Labs., Kanagawa, Japan

Volume

42

Issue

9

fYear

1995

fDate

9/1/1995 12:00:00 AM

Firstpage

1583

Lastpage

1590

Abstract

A new dual poly-Si gate CMOS fabrication process is proposed. The incorporated technology features a boron-penetration-resistant MBN gate structure for pMOSFET´s, and a dual poly-Si gate CMOS process involving separate depositions of in-situ doped n⁺ and p⁺ poly-Si for the nMOS and pMOS gates, 0.2-μm CMOS devices with 3.5-nm gate oxide have been successfully fabricated. The advantages of the new process are demonstrated on these test devices. A CMOS 1/16 dynamic frequency divider fabricated by the new process functions properly up to 5.78 GHz at a 2-V supply voltage

Keywords

CMOS digital integrated circuits; VLSI; frequency dividers; integrated circuit technology; semiconductor doping; 0.2 micron; 2 V; 3.5 nm; 5.78 GHz; MBN gate structure; Si; VLSI; dual-gate CMOS technology; dynamic frequency divider; in-situ doped polysilicon; separate depositions; Boron; CMOS process; CMOS technology; Doping; Fabrication; Frequency conversion; MOS devices; MOSFET circuits; Testing; Voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.405271

Filename

405271