Circuit reliability simulator for interconnect, via, and contact electromigration

Author

Liew, Boon-Khin ; Fang, Peng ; Cheung, Nathan W. ; Hu, Chenming

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Volume

39

Issue

11

fYear

1992

fDate

11/1/1992 12:00:00 AM

Firstpage

2472

Lastpage

2479

Abstract

A model for predicting Al interconnect and intermetallic contact/via electromigration time-to-failure under arbitrary current waveform is incorporated in a circuit electromigration reliability simulator. The simulator can (1) generate layout advisory for width and length of each interconnect, and the number of contacts and vias at each node in a circuit, and (2) estimate the overall circuit electromigration failure rate and/or cumulative percent failure as functions of time, temperature, voltage, frequency, and previous stress (e.g., burn-in)

Keywords

VLSI; aluminium; circuit layout CAD; electromigration; reliability; Al interconnect; MTTF; arbitrary current waveform; circuit reliability simulator; contact electromigration; cumulative percent failure; electromigration reliability simulator; function of frequency; function of previous stress; function of temperature; function of voltage; functions of time; interconnect reliability; layout advisory; overall circuit electromigration failure rate; time-to-failure; via electromigration; Analytical models; Circuit simulation; Computational modeling; Electric breakdown; Electromigration; Frequency estimation; Integrated circuit interconnections; Predictive models; SPICE; Voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.163460

Filename

163460