Title :
Threshold voltage sensitivity of 0.1 μm channel length fully-depleted SOI NMOSFET´s with back-gate bias
Author :
Leobandung, Effendi ; Chou, Stephen Y.
Author_Institution :
Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
fDate :
9/1/1995 12:00:00 AM
Abstract :
We found threshold voltage sensitivity to silicon thickness variation in 0.1 μm channel length fully-depleted SOI NMOSFET´s can be reduced with lightly-doped channel and back-gate bias. However, after the back-interface is accumulated, the reduction is small and threshold voltage roll-off due to high drain bias increases
Keywords :
MOSFET; sensitivity; silicon-on-insulator; 0.1 micron; Si; back-gate bias; fully-depleted SOI NMOSFET; lightly-doped channel; silicon thickness variation; threshold voltage sensitivity; Diodes; Doping; Electron devices; MESFET circuits; MOSFET circuits; RLC circuits; Resonant tunneling devices; Silicon; Solid state circuits; Threshold voltage;
Journal_Title :
Electron Devices, IEEE Transactions on
