An integrated DFT solution for mixed-signal SOCs

Author

Banerjee, Sean ; Mukhopadhyay, Debdeep ; Rao, C.V.G. ; Chowdhury, Dibakar Roy

Author_Institution

Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur

Volume

25

Issue

7

fYear

2006

fDate

7/1/2006 12:00:00 AM

Firstpage

1368

Lastpage

1377

Abstract

This paper introduces an efficient implementation of a test access mechanism (TAM) for mixed-signal system-on-chip (MSOC) testing. The design-for-testability (DFT) strategy has been developed to make the testing of analog cores digitally compliant. The mixed-signal cores have been accessed through specially design mechanisms (switches). A computer-aided test (CAT) tool employing the proposed algorithm has been developed. Extensive experiments have been performed on MSOC benchmarks built of ISCAS´89 circuits for digital cores and ITC´97 circuits for analog cores. Results show that the CAT tool provides a hardware-efficient integrated solution

Keywords

automatic testing; design for testability; electronic engineering computing; integrated circuit testing; mixed analogue-digital integrated circuits; system-on-chip; CAT tool; MSOC testing; VLSI testing; computer-aided test tool; design-for-testability; integrated DFT solution; mixed-signal SOC; test access mechanism; test scheduling; Circuit faults; Circuit testing; Design for testability; Hardware; Integrated circuit testing; Logic testing; Observability; Pins; System testing; System-on-a-chip; DFT for SOCs; VLSI testing; mixed-signal test; test of system on chip; test scheduling;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/TCAD.2005.855972

Filename

1634631