• DocumentCode
    944132
  • Title

    On modulus 8 gateless synchronous scalers with J-K flip-flops

  • Author

    Acha, Jose I. ; Huertas, José L.

  • Author_Institution
    Univesidad de Sevilla, Sevilla, Spain
  • Volume
    64
  • Issue
    3
  • fYear
    1976
  • fDate
    3/1/1976 12:00:00 AM
  • Firstpage
    374
  • Lastpage
    375
  • Abstract
    The problem of finding optimum assignments for a scaler with cycle length 8 is considered. All the possible gateless implementations are obtained by using a computer-aided search. It solves the question about the existence of such an implementation for modulus 8 synchronous scalers.
  • Keywords
    Combinational circuits; Costs; Equations; Feedback; Flip-flops; Gold;
  • fLanguage
    English
  • Journal_Title
    Proceedings of the IEEE
  • Publisher
    ieee
  • ISSN
    0018-9219
  • Type

    jour

  • DOI
    10.1109/PROC.1976.10126
  • Filename
    1454395
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=944132