Title :
High-performance deep-submicrometer Si MOSFETs using vertical doping engineering
Author :
Yan, R.H. ; Lee, K.F. ; Jeon, Duk Young ; Kim, Young-Ok ; Tennant, D.M. ; Chin, Gillian M. ; Morris, M.D. ; Early, K.
Author_Institution :
AT&T Bell Labs., Holmdel, NJ
fDate :
11/1/1992 12:00:00 AM
Abstract :
Summary form only given. Vertical doping engineering was used to implement deep-submicrometer Si MOS devices with excellent room-temperature turn-off and turn-on characteristics, circumventing the conventional scaling obstacles. The vertically engineered doping profile was realized using a 90-keV 1×1013 cm-2 BF 2+ implant for NMOS and a 100-keV 1×1013 cm-2 As+ implant for PMOS, and minimal subsequent thermal treatment, for devices with 0.15-μm minimum effective channel length, 4.0-nm thermally grown gate oxides, and self-aligned silicides on source, drain, and poly-gate. Room-temperature measurements show transconductances of 570/230 μS/μm, threshold voltages of 0.45/-0.3 V, and subthreshold slopes of 84/88 mV/dec for NMOS/PMOS devices with a power supply voltage of 1.5 V
Keywords :
doping profiles; elemental semiconductors; insulated gate field effect transistors; ion implantation; semiconductor doping; silicon; 0.15 micron; 1.5 V; 230 muS; 570 muS; As+ implant; BF2+ implant; NMOS; PMOS; Si:As+; Si:BF2+; deep submicron MOS device; self-aligned silicides; thermally grown gate oxides; vertical doping; vertically engineered doping profile; Doping; Hot carriers; MOSFETs; Microelectronics;
Journal_Title :
Electron Devices, IEEE Transactions on
