Title :
Realisation of three-valued c.m.o.s. cycling gates
Author :
Carmona, J.M. ; Huertas, Jose Luis ; Acha, J.I.
Author_Institution :
Universidad de Sevilla, Dpto. de Electricidad y Electrónica, Facultad de Ciencias, Sevilla, Spain
Abstract :
A new design technique for three-valued cycling operators is presented. The new circuits are shown to be simpler than those previously reported.
Keywords :
field effect integrated circuits; integrated logic circuits; logic gates; ternary logic; inverse cycling gates; logic levels; three valued CMOS cycling gates;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19780196
