Fully parallel superconducting analog-to-digital converter

The authors present measurements that follow up on a design of a 3-b wideband analog-to-digital converter (ADC) given by E. Fang et al. (IEEE Trans. Magn., vol.27, no.3, p.2891-4, 1991). The original design has been modified, and some circuit parameters have been changed to optimize the margins. Based on this modified design, the authors have fabricated and were able to demonstrate the functionality not only of simple logic gates, including inverters, AND, OR, NAND, NOR, and XOR, but also of much more complicated combinations, including a complete 2-b ADC and a complete 3-b binary encoder. After a brief description of the design and modifications, low-speed tests of these circuits are presented and discussed. Simulations have shown that the complete 3-b ADC can work up to 5 GHz.<>