Design of a 16 kbit variable threshold Josephson RAM

Author

Kurosawa, I. ; Takashima, K. ; Nakagawa, H. ; Aoyagi, M. ; Takada, S.

Author_Institution

Electrotech. Lab., Ibaraki, Japan

Volume

3

Issue

1

fYear

1993

fDate

3/1/1993 12:00:00 AM

Firstpage

2675

Lastpage

2678

Abstract

A 16 kb Josephson RAM (random access memory) has been designed using a miniaturized variable threshold memory cell based on a 2 mu m Nb/Al-oxide/Nb junction technology. By using a novel strip-line structure for the inductance of the superconducting quantum interference device (SQUID) type selection gate, the miniaturized cell occupies 14 mm 28 mu m, just 20% of the area of a previous cell designed with a 3 mu m rule. OR-INVERT type address decoders are constructed with a new 4JL (four-junction logic) gate with a fan-out of four. The whole circuit occupies a 3.1 mm*5.0 mm area. The access time is evaluated to be 475 ps, with a total power dissipation of 7.3 mW/chip. Based on these performance data and data from a previous 1 kb RAM experiment, the prospects for Josephson VLSIs are discussed.<>

Keywords

Josephson effect; niobium; random-access storage; superconducting junction devices; superconducting memory circuits; 16 kbit; 2 micron; 475 ps; 7.3 mW; Josephson RAM; Josephson VLSIs; Nb/Al-oxide/Nb junction technology; OR-INVERT type; SQUID; access time; address decoders; four junction logic gate; inductance; random access memory; selection gate; strip-line structure; superconducting quantum interference device; total power dissipation; variable threshold; Decoding; Inductance; Interference; Josephson junctions; Niobium; Random access memory; Read-write memory; SQUIDs; Superconducting devices; Superconducting logic circuits;

fLanguage

English

Journal_Title

Applied Superconductivity, IEEE Transactions on

Publisher

ieee

ISSN

1051-8223

Type

jour

DOI

10.1109/77.233977

Filename

233977