• DocumentCode
    946814
  • Title

    An integrable MOS neuristor line

  • Author

    Kulkarni-Kohli, C. ; Newcomb, R.W.

  • Author_Institution
    University of Maryland, College Park, MD
  • Volume
    64
  • Issue
    11
  • fYear
    1976
  • Firstpage
    1630
  • Lastpage
    1632
  • Abstract
    An integrable MOS design of a neuristor line simulating the conventional properties is presented, the line requiring as few as two sections to simulate the desired properties. In addition the line is low power while consuming no power during the resting state.
  • Keywords
    Aluminum; Capacitance; Circuit simulation; Circuit testing; Equivalent circuits; Etching; MOS capacitors; Pulse circuits; Silicon; Voltage;
  • fLanguage
    English
  • Journal_Title
    Proceedings of the IEEE
  • Publisher
    ieee
  • ISSN
    0018-9219
  • Type

    jour

  • DOI
    10.1109/PROC.1976.10390
  • Filename
    1454659
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=946814