Title :
Margins and yields of SFQ circuits in HTS materials
Author :
Miller, D.L. ; Przybysz, J.X. ; Kang, J.H.
Author_Institution :
Westinghouse Sci. & Technol. Center, Pittsburgh, PA, USA
fDate :
3/1/1993 12:00:00 AM
Abstract :
An analytical model has been developed to project the yield of superconductive integrated circuit chips as a function of circuit operating margins, fabrication process control, and component count. For Gaussian distributed deviations of critical component values from design specifications, chip yield was a highly nonlinear (threshold) function of the ratio of circuit margin to process standard deviation. Computer simulations of single-flux-quantum (SFQ) logic gates with model high-temperature superconductor (HTS) superconductor-normal-metal-superconductor (SNS) junctions operating at GHz clock rates showed at least 50-70% of the margins of similar Nb-Al/sub 2/O/sub 3/-Nb based circuits. Margins and maximum clock rate improved as I/sub c/R/sub n/ (critical-current-normal-resistance product) was increased from 200 to 500 mV.<>
Keywords :
Josephson effect; high-temperature superconductors; modelling; superconducting junction devices; superconducting logic circuits; Gaussian distributed deviations; HTSC; Nb-Al/sub 2/O/sub 3/-Nb based circuits; SFQ circuits; SNS junctions; analytical model; chip yield; circuit operating margins; component count; computer simulation; fabrication process control; gigahertz clock rates; high-temperature superconductor; logic gates; single-flux-quantum; superconductive integrated circuit chips; superconductor-normal-metal-superconductor; yield analysis; Analytical models; Clocks; Fabrication; High temperature superconductors; Integrated circuit modeling; Integrated circuit yield; Process control; Superconducting integrated circuits; Superconducting materials; Superconductivity;
Journal_Title :
Applied Superconductivity, IEEE Transactions on
