DocumentCode :
947571
Title :
FPGA realization of a neural-network-based nonlinear channel equalizer
Author :
Yen, Chin Tsu ; Weng, Wan-de ; Lin, Yen Tsun
Author_Institution :
Graduate Sch. of Eng. & Technol., Nat. Yunlin Univ. of Sci. & Technol., Taiwan
Volume :
51
Issue :
2
fYear :
2004
fDate :
4/1/2004 12:00:00 AM
Firstpage :
472
Lastpage :
479
Abstract :
The software simulation as well as the hardware implementation of equalizers for transmissions through nonlinear communication channels based on artificial neural networks structure is presented in this paper. We consider four-quadrature-amplitude-modulation technique as an example and compare the performance of two different structures of equalizer, namely, the linear least-mean-square-based equalizer (LIN) and the functional link artificial neural networks (FLANN). The learning curve and symbol error rate for the two structures are respectively evaluated by computer simulation. Besides, the systems have been implemented using field-programmable-gate-array devices. As FLANN uses functions to expand the dimensionality of the input signals, it has about the same system complexity as LIN. But FLANN can achieve fast processing speed under parallel processing structure. Simulation results have demonstrated that FLANN presents much better error performance than LIN, especially when the communication channel is highly nonlinear.
Keywords :
equalisers; field programmable gate arrays; least mean squares methods; neural nets; parallel processing; quadrature amplitude modulation; telecommunication channels; FPGA realization; equalizer hardware implementation; error performance; field-programmable-gate-array device; four-quadrature-amplitude-modulation technique; functional link artificial neural network; learning curve; linear least-mean-square-based equalizer; neural-network-based nonlinear channel equalizer; nonlinear communication channel; parallel processing structure; software simulation; symbol error rate; Artificial neural networks; Communication channels; Convergence; Equalizers; Error analysis; Field programmable gate arrays; Multilayer perceptrons; Neural network hardware; Neural networks; Parallel processing;
fLanguage :
English
Journal_Title :
Industrial Electronics, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0046
Type :
jour
DOI :
10.1109/TIE.2004.825221
Filename :
1282036
Link To Document :
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