A switched-capacitor successive-approximation A/D converter

A switched-capacitor successive-approximation analog-to-digital (A/D) converter that incorporates a serial digital-to-analog (D/A) subconverter for generating the threshold voltage sequence is developed. The conversion process is insensitive to parasitic capacitances and offset voltages of the comparator and operational amplifiers. Error analyses and Spice simulations show that a resolution higher than 11 b, a sampling rate up to 440 ksamples/s with 10-b resolution, and a power consumption less than 60 mW are attainable with monolithic implementation using present CMOS technologies. The required chip area is small because of a low device count. The architecture described is therefore best suited for high-accuracy, medium-speed A/D converters in application-specific integrated circuits (ASICs). A prototype converter breadboarded using discrete components has confirmed the principles of operation