Pseudo epi-cost reduction approach and a paradigm shift in substrate material

Author

Aminzadeh, Mehran ; Ravi, K.V. ; Sery, George E. ; Conley, Amiad ; Casperson, Matt

Author_Institution

Intel Corp., Santa Clara, CA, USA

Volume

15

Issue

4

fYear

2002

fDate

11/1/2002 12:00:00 AM

Firstpage

486

Lastpage

492

Abstract

Historically, P/P+ epitaxial wafers have been utilized for CMOS products for more than two decades. The epitaxial wafers have several key characteristics such as latch up immunity, oxygen-free active areas, superior oxide quality, and gettering capability compared to bulk nonepi wafers. The epi wafers, however, are costly. Pseudo epi is an alternative to epi wafers with equivalent device performance and material cost savings of 20%-25%. Pseudo epi or high-temperature hydrogen anneal is expected to save a significant percentage of start material costs over the epi substrate for logic family products where epi wafers have dominated the market.

Keywords

CMOS digital integrated circuits; elemental semiconductors; getters; integrated circuit economics; semiconductor epitaxial layers; silicon; CMOS; P/P+ epitaxial wafers; Si; active areas; digital integrated circuits; gettering; latch up immunity; logic family products; material cost savings; oxide quality; pseudo epi-cost reduction; start material costs; substrate material; Annealing; Costs; Epitaxial layers; Gettering; Hydrogen; Microprocessors; Production facilities; Semiconductor materials; Silicon; Substrates;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/TSM.2002.804891

Filename

1134165