Propagation delay optimisation in multistage GaAs m.e.s.f.e.t. combinational logic circuits by use of dynamic programming

Propagation delays in multistage combinational logic circuits using GaAs metal-semiconductor field-effect transistors (m.e.s.f.e.t.s) are optimised subject to constraints on the overall power dissipation. Specific optimisation criteria are derived for 1-stage, 2-stage, and 3-stage combinational logic circuits. The results are evaluated with parameters of an existing process.