A systolic realization of symmetric block matching algorithm for HD-MAC system

A method for VLSI realization of a symmetric block matching algorithm (SBMA) with systolic array processors is described. The VLSI implementation of the SBMA has some problems because the blocks in the current frame are matched to the averaged blocks of the corresponding previous and next frames. In order o solve such problems, a new error measure with some advantages in terms of real motion and VLSI implementation is proposed. A VLSI architecture for SBMA with the proposed measure is presented. Using this measure, the SBMA was implemented with existing efficient systolic architectures. The proposed measure showed better performance in terms of real motion and insensitivity to noise than the existing one