Title :
Motion estimation architecture for video compression
Author :
Chan, Eric ; Panchanathan, Sethuraman
Author_Institution :
Dept. of Electr. Eng., Ottawa Univ., Ont., Canada
Abstract :
A VLSI architecture which implements the full search block matching motion estimation algorithm in real time is proposed. The architecture consists of a 2D structure of basic cells (BCs), where each BC is capable of computing the mean absolute error. The interblock dependency is exploited and hence the architecture can meet the real-time requirement in various applications. Most importantly, the architecture is simple, modular, and cascadable. This makes possible VLSI implementation as a codec
Keywords :
VLSI; codecs; data compression; motion estimation; video equipment; video signals; 2D structure; VLSI architecture; codec; full search block matching motion estimation algorithm; interblock dependency; mean absolute error; video compression; Broadband communication; Computer architecture; Discrete cosine transforms; HDTV; Hardware; Motion estimation; Redundancy; Transform coding; Very large scale integration; Video compression;
Journal_Title :
Consumer Electronics, IEEE Transactions on
