Title :
SEU resistance in advanced SOI-SRAMs fabricated by commercial technology using a rad-hard circuit design
Author :
Hirose, K. ; Saito, H. ; Kuroda, Y. ; Ishii, S. ; Fukuoka, Y. ; Takahashi, D.
Author_Institution :
Inst. of Space & Astron. Sci., Kanagawa, Japan
fDate :
12/1/2002 12:00:00 AM
Abstract :
We fabricate 128 Kbit SRAMs using a rad-hard circuit design based on a mixed-mode three-dimensional simulation in a commercial silicon-on-insulator foundry with 0.2 μm design rules. Appropriate design increases the critical linear energy transfer of single-event upset over 164.4 MeV/(mg/cm2).
Keywords :
SRAM chips; radiation hardening (electronics); silicon-on-insulator; 0.2 mm; 128 Kbit; SEU resistance; SOI SRAM; fabrication technology; linear energy transfer; mixed-mode three-dimensional simulation; rad-hard circuit design; silicon-on-insulator foundry; Circuit simulation; Circuit synthesis; Energy exchange; Immune system; MOSFETs; Radiation hardening; Silicon on insulator technology; Single event upset; Space technology; Substrates;
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.2002.805978
