• DocumentCode
    949870
  • Title

    Asynchronous rate divider and multiplier designs for LEDR logic

  • Author

    Traver, C. ; Harden, J.C. ; Goodjohn, K. ; Reese, R.B.

  • Author_Institution
    Electr. & Comput. Eng. Dept., Union Coll., Schenectady, NY, USA
  • Volume
    40
  • Issue
    7
  • fYear
    2004
  • fDate
    4/1/2004 12:00:00 AM
  • Firstpage
    414
  • Lastpage
    415
  • Abstract
    Designs for asynchronous circuit modules that allow communication using level encoded dual-rail (LEDR) signalling between two circuits that operate at different computation rates are presented. Signal transition graphs and asynchronous flow tables are used to design these circuits to the gate and transistor level and they are simulated to validate functionality.
  • Keywords
    Petri nets; asynchronous circuits; dividing circuits; integrated circuit design; logic design; multiplying circuits; signal flow graphs; asynchronous circuit modules; asynchronous flow tables; asynchronous rate divider; level encoded dual rail signalling; multiplier designs; signal transition graphs;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20040303
  • Filename
    1283595
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=949870