An area-efficient median filtering IC for image/video applications

An area-efficient IC for high-throughput median filtering applications is presented. This IC implements a modified delete-and-insert sorting algorithm which is very efficient for running order statistics applications. In hardware design, the algorithm is first mapped onto a mapped onto a regular PE (processing element) structure, where each PE consists of shift register, comparator, and some control gates. Then, full-custom circuit/layout design of the PE is conducted to meet the performance requirement. A prototype chip for 64 input samples is implemented and tested. Results show that a clock rate of up to 50 MHz can be achieved using a 1.2 μm CMOS double-metal technology. Two outstanding features of this IC are: any specified order of input pattern can be produced within one clock cycle and each chip can handle at most 64 data and can be cascaded as the number of sorted data is over 64. Thus, this resolved the bottleneck of median search in hardware realization for many system designs, making real-time performance achievable