Title :
An efficient scaling procedure for domain CMOS logic
Author_Institution :
Dept. of Electr. Eng., Alabama Univ., Tuscaloosa, AL, USA
fDate :
9/1/1993 12:00:00 AM
Abstract :
The layout area required by a domino CMOS gate to support a specific response-time performance for a particular capacitive load can be substantially reduced by scaling the NFET chain. A scaling procedure that requires little execution time is described and illustrated by its application to AND, AOI, and OAI domino CMOS gates. The procedure is equally applicable to other forms of dynamics logic
Keywords :
CMOS integrated circuits; integrated logic circuits; logic design; logic gates; CMOS gates; NFET chain; domain CMOS logic; layout area; scaling procedure; CMOS logic circuits; CMOS process; Delay effects; Fabrication; Inverters; Parasitic capacitance; SPICE; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
