Electrical Performance of High-Speed Interconnect Systems

Advancing semiconductor technology is increasing both device densities and speeds. As signal risetimes become faster than Ins and interconnect densities on a single chip carrier approach 500 leads or more, extremely careful electrical modeling of the packaging environment becomes critical. Designers are confronted with the practical problems imposed by the interconnect system which may degrade (or limit) the electrical performance of the device/system. To analyze or design a highspeed, high-density interconnect system, a battery of software modules needs to be developed. Several of these software modules are described.