The Electrical Effect of Single-Chip CMOS Packages

It is becoming increasingly important to understand the electrical effects of packaging before being committed to expensive hardware. Unfortunately, complex and time-consuming computer simulation is necessary to predict accurately the electrical performance of a package system. While this type of analysis must be done during the final stage of the development cycle to ensure an adequate design, a simpler technique is needed in the conceptualization stage. Several generic package designs have been characterized and inserted into two comprehensive simulation models that were operated at various CMOS switching speeds. The results of this detailed study are summarized in a series of charts that correlate relative packaging system noise to both module design and to device speed. In referring to these graphs, the electrical performance of one packaging approach with respect to another can be approximated. This information can be used during the trade-off studies associated with the early phase of development to determine the effect of various design alternatives.