DocumentCode :
952604
Title :
A multiprocessor architecture for Viterbi decoders with linear speedup
Author :
Feygin, Gennady ; Gulak, Patrick G. ; Chow, Paul
Author_Institution :
Dept. of Electr. Eng., Toronto Univ., Ont., Canada
Volume :
41
Issue :
9
fYear :
1993
fDate :
9/1/1993 12:00:00 AM
Firstpage :
2907
Lastpage :
2917
Abstract :
A family of multiprocessor architectures implementing the Viterbi algorithm is presented. The family of architectures is shown to be capable of achieving an increase in throughput that is directly proportional to the number of processors when the number of processors is smaller than the constraint length v of the code. The hardware utilization and the depth of the pipelining available inside each processor are also shown. An architecture with v-1 processors is found to be particularly advantageous, since it results in the maximum speedup and simplest interconnection structure
Keywords :
decoding; pipeline processing; telecommunications computing; Viterbi algorithm; Viterbi decoders; cascade architecture; hardware utilization; linear speedup; multiprocessor architecture; pipelining; Clocks; Computer architecture; Decoding; Digital communication; Digital signal processing; Hardware; Parallel processing; Pipeline processing; Throughput; Viterbi algorithm;
fLanguage :
English
Journal_Title :
Signal Processing, IEEE Transactions on
Publisher :
ieee
ISSN :
1053-587X
Type :
jour
DOI :
10.1109/78.236512
Filename :
236512
Link To Document :
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