Low-power programmable gain CMOS distributed LNA

Author

Zhang, Frank ; Kinget, Peter R.

Author_Institution

Dept. of Electr. Eng., Columbia Univ., New York, NY, USA

Volume

41

Issue

6

fYear

2006

fDate

6/1/2006 12:00:00 AM

Firstpage

1333

Lastpage

1343

Abstract

A design methodology for low power MOS distributed amplifiers (DAs) is presented. The bias point of the MOS devices is optimized so that the DA can be used as a low-noise amplifier (LNA) in broadband applications. A prototype 9-mW LNA with programmable gain was implemented in a 0.18-μm CMOS process. The LNA provides a flat gain, S₂₁, of 8 ± 0.6dB from DC to 6.2 GHz, with an input impedance match, S₁₁, of -16 dB and an output impedance match, S₂₂, of -10 dB over the entire band. The 3-dB bandwidth of the distributed amplifier is 7GHz, the IIP3 is +3 dBm, and the noise figure ranges from 4.2 to 6.2 dB. The gain is programmable from -10 dB to +8 dB while gain flatness and matching are maintained.

Keywords

CMOS integrated circuits; amplification; gain control; low noise amplifiers; programmable circuits; -10 to 8 dB; 16 dB; 18 micron; 4.2 to 6.2 dB; 6.2 GHz; 7 GHz; 9 mW; CMOS process; MOS device; distributed LNA; distributed amplifier; gain flatness; gain matching; impedance match; low noise amplifier; low power CMOS; noise figure; programmable gain; Bandwidth; CMOS process; Design methodology; Distributed amplifiers; Gain; Impedance matching; Low-noise amplifiers; MOS devices; Noise figure; Prototypes; Distributed; low power; low-noise amplifier (LNA); ultrawideband (UWB); variable gain;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2006.874283

Filename

1637598