Title :
Gate capacitances behavior of nanometer FD SOI CMOS devices with HfO2 high-k gate dielectric considering vertical and fringing displacement effects using 2-D Simulation
Author :
Lin, Yu-Sheng ; Lin, Chia-Hong ; Kuo, James B. ; Su, Ke-Wei
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fDate :
6/1/2006 12:00:00 AM
Abstract :
This paper reports the gate-source (drain)/source (drain)-gate capacitance behavior of 100-nm fully depleted silicon-on-insulator CMOS devices with HfO2 high-k gate dielectric considering vertical and fringing displacement effects. Based on the two-dimensional simulation results, a unique two-step CS(D)G/CGS versus VG curve could be identified for the device with the 1.5-nm HfO2 gate dielectric due to the vertical and fringing displacement effects.
Keywords :
MOSFET; capacitance; hafnium compounds; high-k dielectric thin films; semiconductor device models; silicon-on-insulator; 100 nm; FD SOI CMOS devices; HfO2; fringing displacement effects; gate capacitances behavior; high-k gate dielectric; nanometer devices; vertical displacement effects; CMOS technology; Capacitance; Dielectric devices; Dielectric materials; Hafnium oxide; High K dielectric materials; MOS devices; Nanoscale devices; Silicon; Very large scale integration; CMOSFETs; Capacitance; permittivity; silicon-on-insulator (SOI) technology;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2006.874157
