High-level synthesis of data paths for easy testability

The paper presents a method for high-level synthesis of easy testable data paths from a given behavioural description of a design. The synthesis process uses an approach based on a problem-space genetic algorithm (PSGA) to perform integrated scheduling, allocation of testable functional units and registers under area, delay and testability constraints. Testability at behavioural level can be enhanced by minimising the number of self-adjacent registers (self-loops). The main objective is to minimise the testability overhead (area and delay) while searching the design-space to provide a self-loop free architecture. Experiments on benchmarks show that self-loops can be eliminated with minimum additional hardware resources