DocumentCode
955518
Title
Systematic method for synthesising purely delay-insensitive circuits
Author
Huang, C.G. ; Jesshope, C.R. ; Nedelchev, I.M.
Author_Institution
Dept. of Electron. & Electr. Eng., Surrey Univ., Guildford, UK
Volume
140
Issue
5
fYear
1993
fDate
9/1/1993 12:00:00 AM
Firstpage
269
Lastpage
276
Abstract
A novel model for specifying a delay-insensitive circuit is introduced, in which transition signals and two-phase communication convention are used. In this model, a circuit is described by various states. At each state, an input to the circuit not only produces an output, but also causes a corresponding state transition. Based on this model, a systematic method for synthesising purely delay-insensitive circuits is presented, which is suitable for the design of control, data-transmission and data-processing circuits.
Keywords
delays; logic design; data-processing circuits; data-transmission; purely delay-insensitive circuits; state transition; transition signals; two-phase communication;
fLanguage
English
Journal_Title
Computers and Digital Techniques, IEE Proceedings E
Publisher
iet
ISSN
0143-7062
Type
jour
Filename
237920
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