Title :
How does processor MHz relate to end-user performance? II. Memory subsystem and instruction set
Author :
White, Steven W. ; Hester, Phil D. ; Kemp, Jack W. ; McWilliams, G. Jeanette
Author_Institution :
IBM, Austin, TX, USA
Abstract :
For part I, see ibid., vol.13, no.4, p.8-16 (1993). Two processors that compete in the workstation/server markets are compared. The 62.5-MHz IBM RISC System/6000 Model 580 exemplifies a moderate clock rate design. The 133-1200-MHz DEC Alpha processor represents an aggressive clock rate design. The performance implications of the memory subsystems and the effect of instruction sets on path length are described. It is shown that performance measurements on many systems support the initial claim that cycle time is not sufficient to determine performance.<>
Keywords :
computer architecture; microprocessor chips; performance evaluation; reduced instruction set computing; 133 to 1200 MHz; 62.5 MHz; DEC Alpha processor; IBM RISC System/6000 Model 580; cycle time; end-user performance; instruction set; memory subsystem; performance measurements; Clocks; Equations; Instruction sets; Lifting equipment; Performance evaluation; Pipelines; Reduced instruction set computing; Solid modeling; Time measurement; Workstations;
Journal_Title :
Micro, IEEE
