A liftoff process using edge detection (LOPED)

Author

Pai, Pei-Lin ; Oldham, William G.

Author_Institution

Electron. Res. Lab., California Univ., Berkeley, CA, USA

Volume

1

Issue

1

fYear

1988

fDate

2/1/1988 12:00:00 AM

Firstpage

3

Lastpage

9

Abstract

A process for liftoff patterning has been examined with particular emphasis on the process window for manufacturing. Traditional liftoff techniques, which use reentrant resist profiles and evaporation for metal deposition, have the advantage of simplicity and infinite selectivity; however, the need for directional deposition is in conflict with the step coverage requirement of VLSI. A liftoff process using edge detection (LOPED) is described that can pattern thin film deposits with good step coverage. Some guidelines have been developed for the LOPED process to assure successful patterning. A process window is shown as an example for a specific combination of film thicknesses. The potential of the LOPED process is demonstrated for both metallization and trench isolation

Keywords

VLSI; etching; integrated circuit technology; metallisation; semiconductor technology; IC technology; LOPED; VLSI; edge detection; liftoff patterning; liftoff process; metallization; process window; semiconductor technology; step coverage; thin film deposits; trench isolation; Additives; Copper; Dry etching; Image edge detection; Manufacturing processes; Plasma temperature; Resists; Sputtering; Tungsten; Very large scale integration;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/66.4366

Filename

4366