Title :
Application of self-aligned CoSi2 interconnection in submicrometer CMOS transistors
Author :
Broadbent, Eliot K. ; Irani, Rustom F. ; Morgan, Alan E. ; Maillot, Philippe
Author_Institution :
Philips Res. Lab., Sunnyvale, CA, USA
fDate :
11/1/1989 12:00:00 AM
Abstract :
CoSi2 interconnection layers of 0.14-0.40- mu m thickness were applied in a self-aligned manner to 0.75- mu m-gate-length n-channel and p-channel transistors in a complete CMOS device fabrication flow. The sheet resistance above the active regions ranged from 1.6 to as low as 0.46 Omega /square for the four CoSi2 thicknesses examined. Using an Al-Cu/TiW metallization, the resistance per contact for 1- mu m-diameter openings to CoSi2 was + (B)/n and approximately=90% for n+ (As)/p did not adversely affect the measured reverse-bias leakage for transistor gain performance. Furthermore, CoSi2 layers were found compatible with the high-temperature annealing (902 degrees C) of an oxide overlayer, used to achieve some planarization of the device topography, without degradation in electrical performance.
Keywords :
CMOS integrated circuits; cobalt compounds; contact resistance; insulated gate field effect transistors; integrated circuit technology; metallisation; 0.14 to 0.4 micron; 0.75 micron; 902 degC; AlCu-TiW metallization; CoSi2 interconnection layers; contact resistance; gate length; high-temperature annealing; junction consumption; n-channel transistors; oxide overlayer; p-channel transistors; planarization; reverse-bias leakage; self-alignment; sheet resistance; silicide formation; submicrometer CMOS transistors; thickness; transistor gain performance; Annealing; Contact resistance; Degradation; Fabrication; Gain measurement; Metallization; Performance gain; Planarization; Silicides; Surfaces;
Journal_Title :
Electron Devices, IEEE Transactions on
