DocumentCode :
956071
Title :
Efficient architectures for 1-D and 2-D lifting-based wavelet transforms
Author :
Liao, Hongyu ; Mandal, Mrinal Kr ; Cockburn, Bruce F.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Alberta, Edmonton, Alta., Canada
Volume :
52
Issue :
5
fYear :
2004
fDate :
5/1/2004 12:00:00 AM
Firstpage :
1315
Lastpage :
1326
Abstract :
The lifting scheme reduces the computational complexity of the discrete wavelet transform (DWT) by factoring the wavelet filters into cascades of simple lifting steps that process the input samples in pairs. We propose four compact and efficient hardware architectures for implementing lifting-based DWTs, namely, one-dimensional (1-D) and two-dimensional (2-D) versions of what we call recursive and dual scan architectures. The 1-D recursive architecture exploits interdependencies among the wavelet coefficients by interleaving, on alternate clock cycles using the same datapath hardware, the calculation of higher order coefficients along with that of the first-stage coefficients. The resulting hardware utilization exceeds 90% in the typical case of a five-stage 1-D DWT operating on 1024 samples. The 1-D dual scan architecture achieves 100% datapath hardware utilization by processing two independent data streams together using shared functional blocks. The recursive and dual scan architectures can be readily extended to the 2-D case. The 2-D recursive architecture is roughly 25% faster than conventional implementations, and it requires a buffer that stores only a few rows of the data array instead of a fixed fraction (typically 25% or more) of the entire array. The 2-D dual scan architecture processes the column and row transforms simultaneously, and the memory buffer size is comparable to existing architectures.
Keywords :
computational complexity; discrete wavelet transforms; filtering theory; higher order statistics; recursive estimation; signal representation; signal sampling; 1D lifting-based wavelet transforms; 2D lifting-based wavelet transforms; DWT; alternate clock cycles; buffer size; computational complexity; datapath hardware utilization; discrete wavelet transforms; dual scan architectures; higher order coefficients; independent data streams; lifting scheme; recursive architectures; Clocks; Computational complexity; Computer architecture; Discrete wavelet transforms; Filters; Hardware; Interleaved codes; Two dimensional displays; Wavelet coefficients; Wavelet transforms;
fLanguage :
English
Journal_Title :
Signal Processing, IEEE Transactions on
Publisher :
ieee
ISSN :
1053-587X
Type :
jour
DOI :
10.1109/TSP.2004.826175
Filename :
1284829
Link To Document :
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