Title :
COMPACTEST: a method to generate compact test sets for combinational circuits
Author :
Pomeranz, Irith ; Reddy, Lakshmi N. ; Reddy, Sudhakar M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
fDate :
7/1/1993 12:00:00 AM
Abstract :
Heuristics to aid the derivation of small test sets that detect single stuck-at faults in combinational logic circuits are proposed. The heuristics can be added to existing test pattern generators without compromising fault coverage. Experimental results obtained by adding the proposed heuristics to a simple PODEM procedure and applying it to the ISCAS-85 and fully-scanned ISCAS-89 benchmark circuits are presented to substantiate the effectiveness of the proposed heuristics
Keywords :
combinatorial circuits; fault location; integrated logic circuits; logic testing; ISCAS-85; PODEM procedure; combinational circuits; compact test sets; fault coverage; fully-scanned ISCAS-89 benchmark circuits; heuristics; logic circuits; single stuck-at faults; test pattern generators; Benchmark testing; Circuit faults; Circuit testing; Cities and towns; Combinational circuits; Compaction; Electrical fault detection; Fault detection; Logic testing; Performance evaluation;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
