Title :
3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
fDate :
7/1/1993 12:00:00 AM
Abstract :
A method for weighted pseudorandom test generation based on a deterministic test set is described. The main advantages of the method described over existing methods are: (1) only three easily generated weights (0, 0.5 and 1) are used, (2) a minimum number of shift register cells is used, thus leading to minimal hardware for built-in-test applications, and (3) the weights are selected to allow the same coverage of target faults attained by the deterministic test set to be attained by weighted random patterns. The weights are computed by walking through the range of test generation approaches from pure random at one extreme to deterministic at the other extreme, dynamically selecting the weight assignments to correspond to the remaining faults at every stage. Hardware suitable for the generation of random patterns under the proposed method is described. The method is suitable for both combinational and sequential circuits. Experimental results are provided for ISCAS-85 and MCNC benchmark circuits
Keywords :
built-in self test; combinatorial circuits; integrated logic circuits; logic testing; sequential circuits; ISCAS-85; MCNC benchmark circuits; built-in-test applications; combinational circuits; deterministic test set; pseudo-random test generation; sequential circuits; shift register cells; target faults; weight assignments; weighted random patterns; Automatic test pattern generation; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Hardware; Random number generation; Sequential analysis; Sequential circuits; Test pattern generators;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
