Title :
Another design of the successive approximation register for A/D converters
Author_Institution :
University of Tasmania, Hobart, Australia
fDate :
5/1/1979 12:00:00 AM
Abstract :
An alternative design of the successive approximation register is proposed. The design eliminates the dual flip-flop outputs of previous designs.
Keywords :
Attenuation; Clocks; Delay; Digital filters; Filtering; Flip-flops; Frequency; Information science; Logic design; Logic devices;
Journal_Title :
Proceedings of the IEEE
DOI :
10.1109/PROC.1979.11341
