DocumentCode
956696
Title
PELOX integrated PBL
Author
Roth, S.S. ; Cooper, K.J. ; Kirsch, H.C. ; Ray, W. ; Hendrix, L. ; Simon, G.
Author_Institution
Motorola, Austin, TX, USA
Volume
6
Issue
3
fYear
1993
fDate
8/1/1993 12:00:00 AM
Firstpage
246
Lastpage
250
Abstract
Polysilicon buffered LOCOS (PBL) does not exhibit sufficient field oxide recess to support aggressive device scaling without the introduction of processes which are difficult to control. Recently, polysilicon encapsulated local oxidation (PELOX) has been proposed as an easily scaled isolation technique that exhibits LOCOS equivalent recess. The integration of PELOX into an existing PBL 1-Mb DRAM baseline process is described. PELOX-integrated PBL (PIPBL) is demonstrated to enhance final field oxide recess without increasing encroachment. The improved final field oxide recess is shown to provide increased process margin as evidenced by superior probe yield
Keywords
DRAM chips; integrated circuit technology; oxidation; DRAM baseline process; final field oxide recess; isolation technique; polysilicon buffered LOCOS; polysilicon encapsulated local oxidation; probe yield; process margin; Buffer layers; Capacitors; Fabrication; Hafnium; Oxidation; Probes; Random access memory; Robustness; Stress; Substrates;
fLanguage
English
Journal_Title
Semiconductor Manufacturing, IEEE Transactions on
Publisher
ieee
ISSN
0894-6507
Type
jour
DOI
10.1109/66.238172
Filename
238172
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