A New Gate-Charging Protection Strategy for Transistors in Integrated-Circuit Test Chips and Products

This paper presents a new gate-charging protection strategy for transistors in integrated-circuit (IC) test chips and products. The strategy, using a low-threshold-voltage protection device (PD) of the highest voltage class (i.e., with the thickest available gate oxide) in any given process technology, is capable of providing full charging protection for transistors of all voltage classes during back-end plasma-involved manufacturing process. In conjunction with a method that globally turns off the PDs, the strategy also minimizes the protection-device-induced leakages during electrical tests or circuit operation. This new gate-charging protection strategy can benefit the design and manufacturing for the next-generation IC test chips and products, in particular for circuit products emphasized on low voltage and current and low power consumption.