The design, fabrication and test of 16k bubble memory chips

The design considerations, fabrication steps and test results are described for a 16K bit, major-minor loop bubble memory chip with an active area of 0.02 in². The design includes a thin film chevron expanded detector and a double Y-bar transfer gate which does not require electrical insulation and which has been fabricated permalloy-first. The circuit has been successfully tested at 100 KHz using YEuTm as the bubble material. The transfer gate with a margin of 5 Oe at a rotating field of 40 Oe limits performance.