Reliable and fast reconfigurable hierarchical interconnection networks for linear WSI arrays

Author

Sul, C. ; McLeod, R.D. ; Pedrycz, W.

Author_Institution

Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada

Volume

1

Issue

2

fYear

1993

fDate

6/1/1993 12:00:00 AM

Firstpage

224

Lastpage

228

Abstract

A self-pruning binary tree (SPBT) interconnection network architecture that tolerate faults in a wafer scale integration (WSI) environment is proposed. The goal of the SPBT network is to provide a reliable and a quickly reconfigured interconnection network architecture for linear WSI arrays. The proposed architecture uses a bottom-up approach to reconfigure a linear pipelined array on a potentially defective WSI array using a binary tree interconnection scheme. The binary tree is generated by successive formation of hierarchical modules. For N processing elements (PEs) on the wafer, reconfiguration time is O(log N). The propagation delay is bounded by Theta (log N) and is independent of the number of faulty PEs. Faults in the switching network as well as faulty processing elements are tolerated.<>

Keywords

VLSI; built-in self test; systolic arrays; SPBT network; binary tree interconnection scheme; bottom-up approach; hierarchical modules; linear WSI arrays; linear pipelined array; processing elements; propagation delay; reconfigurable hierarchical interconnection networks; reconfiguration time; self-pruning binary tree; switching network; Assembly systems; Binary trees; Costs; Delay; Logic arrays; Multiprocessor interconnection networks; Nearest neighbor searches; Testing; Very large scale integration; Wafer scale integration;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/92.238412

Filename

238412