Title :
A design of a fast and area efficient multi-input Muller C-element
Author :
Wuu, Tzyh-Yung ; Vrudhula, Sarma B K
Author_Institution :
Inf. Sci. Inst., Univ. of Southern California, Los Angeles, CA, USA
fDate :
6/1/1993 12:00:00 AM
Abstract :
A multi-input Muller C-element has frequently been used for joining signal transitions or completion time detection in self-timed circuits. An n-input Muller C-element design which uses the multilevel logic design technique and has a symmetric format for any integer n >or=2 is presented. In comparison with series-parallel MOS structure implementations and C-element tree implementations, the present design has fewer restrictions in terms of n, less path delay, less delay variance from inputs to output, and less area consumption. Experimental validation based on an industrial standard cell library is presented.<>
Keywords :
CMOS integrated circuits; integrated logic circuits; invertors; logic design; many-valued logics; area consumption; area efficient multi-input Muller C-element; completion time detection; delay variance; industrial standard cell library; multilevel logic design; path delay; self-timed circuits; signal transitions; symmetric format; Circuits; Delay; Equations; Information science; Latches; Signal generators; Strontium; Timing; Tree data structures; Very large scale integration;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
