Title :
Parallel-concurrent fault simulation
Author_Institution :
Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
Abstract :
A new parallel-concurrent fault simulation algorithm based on the partitioning of faults into groups, with the group size equal to the number of bits in the host computer word, is presented. The fault effects of a particular group are evaluated using parallel fault simulation techniques and propagated using concurrent fault simulation techniques. The speed of the algorithm depends on the circuit and on the fault-grouping criterion. An automatic grouping criterion is devised to group faults that are "close" or nearly equivalent. Comparisons to the concurrent, to the deductive, and to the PROOFS fault simulation techniques are performed on a SPARC SLC with 16 MB of memory running UNIX. ISCAS89 benchmark circuits are used for this comparison.<>
Keywords :
VLSI; digital simulation; fault location; integrated logic circuits; logic CAD; parallel algorithms; ISCAS89 benchmark circuits; SPARC SLC; UNIX; automatic grouping criterion; fault-grouping criterion; group size; host computer word; logic CAD; parallel-concurrent fault simulation algorithm; partitioning; Associate members; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Computer simulation; Concurrent computing; Digital circuits; Logic circuits; Very large scale integration;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
