DocumentCode :
958273
Title :
Capacitor-coupled logic using GaAs depletion-mode f.e.t.s
Author :
Mellor, P.J.T. ; Livingstone, A.W.
Author_Institution :
Post Office Research Centre, Ipswich, UK
Volume :
16
Issue :
19
fYear :
1980
Firstpage :
749
Lastpage :
750
Abstract :
A new method of interconnecting depletion-mode GaAs f.e.t. logic stages, using capacitive coupling, eliminates the need for a negative power supply and is more tolerant of processing spreads, particularly of pinch-off voltage. The technique may be combined with conventional level shifting, operating at very low current. The use of capacitance may be extended to achieve clocked dynamic data storage with very low power dissipation.
Keywords :
III-V semiconductors; Schottky gate field effect transistors; field effect integrated circuits; gallium arsenide; integrated logic circuits; shift registers; GaAs depletion mode FET; capacitor coupled logic; clocked dynamic data storage; level shifting; shift registers;
fLanguage :
English
Journal_Title :
Electronics Letters
Publisher :
iet
ISSN :
0013-5194
Type :
jour
DOI :
10.1049/el:19800532
Filename :
4244308
Link To Document :
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