Title :
Capacitor-coupled logic using GaAs depletion-mode f.e.t.s
Author :
Mellor, P.J.T. ; Livingstone, A.W.
Author_Institution :
Post Office Research Centre, Ipswich, UK
Abstract :
A new method of interconnecting depletion-mode GaAs f.e.t. logic stages, using capacitive coupling, eliminates the need for a negative power supply and is more tolerant of processing spreads, particularly of pinch-off voltage. The technique may be combined with conventional level shifting, operating at very low current. The use of capacitance may be extended to achieve clocked dynamic data storage with very low power dissipation.
Keywords :
III-V semiconductors; Schottky gate field effect transistors; field effect integrated circuits; gallium arsenide; integrated logic circuits; shift registers; GaAs depletion mode FET; capacitor coupled logic; clocked dynamic data storage; level shifting; shift registers;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19800532