BiMOS transistors: merged bipolar/sidewall MOS transistors

Summary form only given. A technique to form device structures which merge MOS and bipolar transistors into bipolar/sidewall MOS transistors (BiMOS) is discussed. The concept and feasibility of this technique are demonstrated by fabricating and DC-characterizing the merged structures. The merged bipolar/sidewall MOS structures are formed by growing a gate oxide layer on the sidewalls of the mesa (exposed p-n junction) and depositing a polysilicon layer on the oxide to form semivertical MOS structures. Following this, the polysilicon layer is patterned and etched, and the samples are patterned and implanted to form n⁺ and p⁺ drains and sources of the sidewall MOS transistors. Using this technique, many of the typical BiCMOS subcircuit elements, such as MOS-bipolar Darlington structures (with a MOS input), can be formed. The advantage of these merged structures is that they occupy an area approximately the same as that of a bipolar transistor, while performing the functions of circuit elements composed of two transistors.